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| PRELIMINARY TECHNICAL DATA a Preliminary Technical Data FEATURES Pin Programmable 1, 2 or 3 Phase Operation Excellent Static and Dynamic Current Sharing Superior Load Transient Response when used with ADOPTTM Optimal Positioning Technology Noise-Blanking for Speed and Stability Synchronous Rectification Control for Optimized Light Load Efficiency Soft DAC Output Voltage Transition for VID Change Cycle-by-Cycle Current Limiting Latched or Hiccup Current Overload Protection Masked Power Good during Output Voltage Transients Soft Start-up without Power-On In-Rush Current Surge Two Level Over-Voltage and Reverse-Voltage Protection APPLICATIONS Next Generation Intel Mobile CPU Core DC/DC Converters Programmable Output Power Supplies Multi-Phase Core Controller for Intel(R) Mobile CPUs ADP3205 GENERAL DESCRIPTION The ADP3205 is a 1, 2, or 3 phase hysteretic peak current mode DC-DC buck converter controller dedicated to power a mobile processor's core. The chip optimized low voltage design runs from the 3.3 V system supply. The chip contains a precision 6-bit DAC whose nominal output voltage is set by VID code. The ADP3205 features high-speed operation to allow a minimized inductor size that results in the fastest change of current to the output. To further minimize the number of output capacitors, the converter features active voltage positioning enhanced with ADOPT optimal compensation to ensure a superior load transient response. The output signals interface with ADP3415 MOSFET drivers that are optimized for high speed and high efficiency. The ADP3205 is capable of providing synchronous rectification control to extend battery lifetime in light load conditions. FUNCTIONAL BLOCK DIAGRAM DRV3 DRVSD3 39 38 DRV2 37 DRVSD2 36 DRV1 DRVSD1 35 34 ADP3205 TSYNC 40 PSI HYSSET CLIM/ZCS CMP 33 CS3 CS2 CS1 CS+ VDACREF HYSTERESIS SET & CLIM SET VBG HYS/CLIM CONTROL & CS MUX/ PHASE CONTROL CURRENT SENSE MUX CSCORE CMP RAMP REG DPSHIFT SET BOOT DPSHIFT DRVCTRL DPSLP VREF BOOTSET DPRSET DPRSLP VID5 VID4 VID3 VID2 VID1 VID0 PWRGD CLKEN TPWRGD DPWRGD BOOT SS 19 VREF VBG REF MUX DACREF DACREFB DAC RES NETWORK DAC REF DIVIDER CORE ABOVE CMP VREF VBG PRWGD MASKING MASK PWRGD LATCH DRVCTRL COREGD EOFSS ALARM LATCHEN CORE BELOW CMP COREFB PRWGD DELAY ALARM CONTROL DVP CMP OVP LATCH VOV SS/LATCH-OFF TIMER SD VCC GND 22 UVLO CMP BIAS ENABLER ALARM RST BANDGAP & REFAMP VREF VBG RST RVP LATCH RVP CMP VRV CLAMP ADOPT is a trademark of Analog Devices REV. PrK 10/23/02 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel:781/329-4700 www.analog.com Fax:781/326-8703 (c)ANALOG DEVICES, INC., 2002 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. |
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